Quantum Hardware
DFT-Guided Co-Optimization of Valley Splitting and Spin Coherence in Si/SiGe Quantum Wells Reveals a 3–4 nm Design Sweet Spot
A fundamental trade-off exists in Si/SiGe quantum well design for spin qubits: narrowing the well increases valley splitting but pushes more of the electron wavefunction into the SiGe buffer, amplifying hyperfine coupling to ⁷³Ge and degrading spin coherence. Using density functional theory on reali…
MoSi Stoichiometry Optimization Unlocks Peak SNSPD Sensitivity via Low-Tc, High-Rs Film Engineering
This study systematically maps how MoSi thin-film stoichiometry governs SNSPD performance, revealing a universal scaling behavior across critical temperature (Tc), sheet resistance (Rs), and film thickness. The optimal composition — Mo₀.₅₃Si₀.₄₇ at 5.4 nm thickness — achieves the highest sensitivity…
SFQ-Programmable Millikelvin DACs Enable Scalable, Coherence-Preserving Control of Superconducting Qubits
A team has demonstrated a superconducting digital-to-analog converter (DAC) operating at millikelvin temperatures, integrated directly with high-coherence fluxonium qubits in a multi-chip module. The DAC generates persistent analog flux signals for qubit parameter tuning and is programmed via single…
FPGA Accelerates Quantum LDPC Decoding
IBM has developed an FPGA-based Relay-BP decoder for quantum Low-Density Parity-Check (qLDPC) codes, demonstrating significant speed improvements over GPU-based solutions. This advancement enables real-time decoding on hardware, which is crucial for practical quantum error correction.